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CS43L21
Low Power, Stereo Digital to Analog Converter
FEATURES
98 dB Dynamic Range (A-wtd) -86 dB THD+N Headphone Amplifier - GND Centered - On-Chip Charge Pump Provides -VA_HP - No DC-Blocking Capacitor Required - 46 mW Power Into Stereo 16 @ 1.8 V - 88 mW Power Into Stereo 16 @ 2.5 V - -75 dB THD+N Digital Signal Processing Engine - Bass & Treble Tone Control, De-Emphasis - PCM Mix w/Independent Vol Control - Master Digital Volume Control and Limiter - Soft Ramp & Zero Cross Transitions Beep Generator - Tone Selections Across Two Octaves - Separate Volume Control - Programmable On & Off Time Intervals - Continuous, Periodic or One-Shot Beep Selections Programmable Peak-Detect and Limiter Pop and Click Suppression
SYSTEM FEATURES
24-bit Conversion 4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation - Stereo Playback: 12.93 mW @ 1.8 V Variable Power Supplies - 1.8 V to 2.5 V Digital & Analog - 1.8 V to 3.3 V Interface Logic Power Down Management Software Mode (IC(R) & SPITM Control) Hardware Mode (Stand-Alone Control) Digital Routing/Mixes: - Mono Mixes Flexible Clocking Options - Master or Slave Operation - High-Impedance Digital Output Option (for easy MUXing between DAC and Other Data Sources) - Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz)
1.8 V to 3.3 V
1.8 V to 2.5 V
1.8 V to 2.5 V
PCM Serial Interface
Serial Audio Input Hardware Mode or I2C & SPI Software Mode Control Data Level Translator
MUX
Beep Generator
Digital Signal Processing Engine
MUX
Multibit Modulator
Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter
Headphone Amp - GND Centered Headphone Amp - GND Centered Charge Pump
Left HP Out
Right HP Out
Reset
Register Configuration
Advance Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
JULY '06 DS723A1
CS43L21
APPLICATIONS
Portable Audio Players MD Players PDAs Personal Media Players Portable Game Consoles Smart Phones Wireless Headsets
GENERAL DESCRIPTION
The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS43L21 operates from a low-voltage analog and digital core, making this DAC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS43L21 is available in a 32-pin QFN package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CS43L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 63 for complete details.
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CS43L21
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 12 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 13 LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 14 HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 15 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 16 SWITCHING SPECIFICATIONS - IC(R) CONTROL PORT .................................................................. 18 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT ............................................................ 19 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 20 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 20 POWER CONSUMPTION .................................................................................................................... 21 4. APPLICATIONS ................................................................................................................................... 22 4.1 Overview ......................................................................................................................................... 22 4.1.1 Architecture ........................................................................................................................... 22 4.1.2 Line & Headphone Outputs ................................................................................................... 22 4.1.3 Signal Processing Engine ..................................................................................................... 22 4.1.4 Beep Generator ..................................................................................................................... 22 4.1.5 Device Control (Hardware or Software Mode) ...................................................................... 22 4.1.6 Power Management .............................................................................................................. 22 4.2 Hardware Mode .............................................................................................................................. 23 4.3 Analog Outputs ............................................................................................................................... 24 4.3.1 De-Emphasis Filter ................................................................................................................ 24 4.3.2 Volume Controls .................................................................................................................... 25 4.3.3 Mono Channel Mixer ............................................................................................................. 25 4.3.4 Beep Generator ..................................................................................................................... 25 4.3.5 Tone Control .......................................................................................................................... 26 4.3.6 Limiter .................................................................................................................................... 26 4.3.7 Line-Level Outputs and Filtering ........................................................................................... 27 4.3.8 On-Chip Charge Pump .......................................................................................................... 28 4.4 Serial Port Clocking ........................................................................................................................ 28 4.4.1 Slave ..................................................................................................................................... 29 4.4.2 Master ................................................................................................................................... 29 4.4.3 High-Impedance Digital Output ............................................................................................. 30 4.4.4 Quarter- and Half-Speed Mode ............................................................................................. 30 4.5 Digital Interface Formats ................................................................................................................ 30 4.6 Initialization ..................................................................................................................................... 31 4.7 Recommended Power-Up Sequence ............................................................................................. 31 4.8 Recommended Power-Down Sequence ........................................................................................ 32 4.9 Software Mode ............................................................................................................................... 33 4.9.1 SPI Control ............................................................................................................................ 33 4.9.2 IC Control ............................................................................................................................. 33 4.9.3 Memory Address Pointer (MAP) ............................................................................................ 35 4.9.3.1 Map Increment (INCR) ............................................................................................... 35 5. REGISTER QUICK REFERENCE ........................................................................................................ 36 6. REGISTER DESCRIPTION .................................................................................................................. 39 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39 DS723A1 3
CS43L21
6.2 Power Control 1 (Address 02h) ...................................................................................................... 39 6.3 Speed Control (Address 03h) ......................................................................................................... 40 6.4 Interface Control (Address 04h) ..................................................................................................... 41 6.5 DAC Output Control (Address 08h) ................................................................................................ 41 6.6 DAC Control (Address 09h) ............................................................................................................ 42 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 44 6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 45 6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46 6.10 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 47 6.11 Tone Control (Address 15h) ......................................................................................................... 48 6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49 6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 49 6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 50 6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 51 6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 52 6.17 Status (Address 20h) (Read Only) ............................................................................................... 52 6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 53 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 54 7.1 Headphone THD+N versus Output Power Plots ............................................................................ 54 7.2 Headphone Amplifier Efficiency ...................................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS ........................................................................................................ 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 63
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LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Headphone Output Test Load ..................................................................................................... 15 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17 Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17 Figure 6.Control Port Timing - IC ............................................................................................................. 18 Figure 7.Control Port Timing - SPI Format ................................................................................................ 19 Figure 8.Output Architecture ..................................................................................................................... 24 Figure 9.De-Emphasis Curve .................................................................................................................... 25 Figure 10.Beep Configuration Options ...................................................................................................... 26 Figure 11.Peak Detect & Limiter ............................................................................................................... 27 Figure 12.Master Mode Timing ................................................................................................................. 29 Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30 Figure 14.IS Format ................................................................................................................................. 30 Figure 15.Left-Justified Format ................................................................................................................. 31 Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31 Figure 17.Initialization Flow Chart ............................................................................................................. 32 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 33 Figure 19.Control Port Timing, IC Write ................................................................................................... 34 Figure 20.Control Port Timing, IC Read ................................................................................................... 34 Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16 load) .................................................... 54 Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16 load) .................................................... 54 Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32 load) .................................................... 55 Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32 load) .................................................... 55 Figure 25.Power Dissipation vs. Output Power into Stereo 16 ......................................................................56 Figure 26.Power Dissipation vs. Output Power into Stereo 16 (Log Detail) .......................................... 56 Figure 27.Passband Ripple ....................................................................................................................... 60 Figure 28.Stopband ................................................................................................................................... 60 Figure 29.Transition Band ......................................................................................................................... 60 Figure 30.Transition Band (Detail) ............................................................................................................ 60
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 23 Table 3. MCLK/LRCK Ratios .................................................................................................................... 29
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CS43L21 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
TSTO(M/S)
DGND
MCLK
SCLK
SDIN
VD
32
31
30
29
28
27
26
VL
LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (IS/LJ) ADO/CS (DEM) VA_HP FLYP GND_HP FLYN
RESET
25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
TSTO TSTO TSTO TSTO TSTO TSTO TSTO TSTO
CS43L21
21 20 19 18 17
AOUTA
VSS_HP
AOUTB
AGND
Pin Name
LRCK SDA/CDIN (MCLKDIV2)
#
1
Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port.
2
SCL/CCLK (IS/LJ)
3
Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface formats for the DAC. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip-select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.
AD0/CS (DEM) VA_HP FLYP GND_HP FLYN VSS_HP
4 5 6 7 8 9
Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section.
6
FILT+
NIC
VA
VQ
DS723A1
CS43L21
AOUTB AOUTA VA AGND FILT+ VQ NIC TSTO TSTO TSTO TSTO TSTO TSTO RESET VL VD DGND TSTO (M/S) MCLK SCLK SDIN Thermal Pad 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left "floating". No other external connection should be made to this pin. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. 30 31 32 Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Thermal relief pad for optimized heat dissipation. See "QFN Thermal Pad" on page 59.
29
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CS43L21
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW)
RESET SCL/CCLK (IS/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK TSTO (M/S) SDIN
I/O
Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input
Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS Table 1. I/O Power Rails
Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V
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CS43L21 2. TYPICAL CONNECTION DIAGRAMS
+1.8 V or +2.5 V
1 F 0.1 F 0.1 F 0.1 F
See Note 3
+1.8 V or +2.5 V
1 F
Note 3: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output .
VD
VA
VA_HP AOUTB
1.5 F
See Note 4
**
1 F
**
FLYP FLYN VSS_HP AOUTA
0.022 F 51.1
Headphone Out Left & Right
1.5 F
**
1 F
**
GND_HP
* *Use low ESR ceramic capacitors.
470 C Rext Line Level Out Left & Right See Note 2
CS43L21
470
C
Rext
Speaker Driver
Note 4 : Larger capacitors, such as 1.5 F, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default.
Note 2 : For best response to Fs/2 :
C=
MCLK SCLK LRCK Digital Audio Processor SDIN RESET SCL/CCLK SDA/CDIN AD0/CS
Rext + 470 4Fs(Rext x 470 )
This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations.
2k
2k
+1.8 V, +2.5 V or +3.3 V
See Note 1
VL
0.1 F
Note 1: Resistors are required for IC control port operation
FILT+
1 F
AGND
1 F
VQ DGND
Figure 1. Typical Connection Diagram (Software Mode)
DS723A1
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CS43L21
+1.8V or +2.5V
1 F 0.1 F 0.1 F 0.1 F 1 F
See Note 1
+1.8V or +2.5V
VD
VA
VA_HP AOUTB
Note 1: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output .
1 F
**
FLYP FLYN AOUTA
0.022 F 51.1
Headphone Out Left & Right
1 F
**
VSS_HP GND_HP
470 C
Rext Line Level Out Left & Right See Note 2
* *Use low ESR ceramic capacitors.
CS43L21
470
C
Rext
MCLK SCLK LRCK SDIN VL or DGND Digital Audio Processor
47 k
See Note 3
Speaker Driver
TSTO/M/S RESET IS/LJ MCLKDIV2 DEM AGND
1 F
FILT+
1 F
+1.8V, 2.5 V or +3.3V
0.1 F
VL VQ DGND
k Note 3: Pull-up to VL (47 k Master Mode. Pullfor down to DGND for Slave Mode. Note 2 : This circuitry is intended for applications where the CS 43L21 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . For best response to Fs/2 :
C=
Rext + 470 4Fs (Rext x 470 )
Figure 2. Typical Connection Diagram (Hardware Mode)
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DS723A1
CS43L21 3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.) Parameters
DC Power Supply (Note 1) Analog Core Headphone Amplifier Digital Core Serial/Control Port Interface Ambient Temperature Commercial - CNZ Automotive - DNZ VA VA_HP VD VL TA 1.65 2.37 1.65 2.37 1.65 2.37 1.65 2.37 3.14 -10 -40 1.8 2.5 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85 V V V V V V V V V C C
Symbol
Min
Nom
Max
Units
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply
Symbol
Min
-0.3 -0.3 -0.3 -0.3 -50 -65
Max
3.0 3.0 4.0 10 VL+ 0.4 +115 +150
Units
V V V mA V C C
Analog VA, VA_HP VD Digital VL Serial/Control Port Interface (Note 2) Iin VIND TA Tstg
Input Current Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
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CS43L21 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
Parameter (Note 4)
VA = 2.5V (nominal) VA = 1.8V (nominal) Min Typ Max Min Typ Max
Unit
RL = 10 k Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -78 -88 -72 -32 -88 -70 -30 -82 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB
16-Bit
RL = 16
Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -69 -75 -72 -32 -75 -70 -30 -69 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB
16-Bit
Other Characteristics for RL = 16 or 10 k
Output Parameters (Note 5) 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on page 14 Refer to Table "Headphone Output Power Characteristics" on page 15 80 80 95 93 (Note 6) (Note 6) 16 0.1 100 0.25 150 16 0.1 100 0.25 150
Full-scale Output Voltage (2*G*MI*VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 10 k
Vpp mW dB dB dB ppm/ C pF
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DS723A1
CS43L21 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
Parameter (Note 4)
VA = 2.5V (nominal) Min Typ Max
VA = 1.8V (nominal) Min Typ Max
Unit
RL = 10 k Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -73 -88 -72 -32 -88 -70 -30 -80 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB
16-Bit
RL = 16 Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -67 -75 -72 -32 -75 -70 -30 -67 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB
16-Bit
Other Characteristics for RL = 16 or 10 k
Output Parameters (Note 5) 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on page 14 Refer to Table "Headphone Output Power Characteristics" on page 15 80 80 95 93 (Note 6) (Note 6) 16 0.1 100 0.25 150 16 0.1 100 0.25 150
Full-scale Output Voltage (2*G*MI*VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 10 k
Vpp mW dB dB dB ppm/ C pF
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CS43L21 LINE OUTPUT VOLTAGE CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF (see Figure 3).
Parameter
VA = 2.5V (nominal) Min Typ Max
Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.95 1.34 1.34 1.55 1.55 1.73 1.73 2.05 2.05 2.41 2.41 2.85 2.85 3.39 3.39 (See (Note 7) 3.88 2.15 -
VA = 1.8V (nominal) Min Typ Max
Unit
AOUTx Voltage Into RL = 10 k
HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111
1.41 -
0.97 0.97 1.12 1.12 1.25 1.25 1.48 1.48 1.73 1.73 2.05 2.05 2.44 2.44 2.79 2.79
1.55 -
Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp
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DS723A1
CS43L21 HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 , CL = 10 pF (see Figure 3).
Parameter
VA = 2.5V (nominal) Min Typ Max
Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430
VA = 1.8V (nominal) Min Typ Max
Unit
AOUTx Power Into RL = 16
HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 14 14 19 19 23 23 (Note 7) 32 (Note 7) 44 (Note 5, 7) 7 7 10 10 12 12 17 17 23 23 (Note 5) 32 mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms
4. One-half LSB of triangular PDF dither is added to data. 5. Full-scale output voltage and power is determined by the gain setting, G, in register "Headphone Analog Gain (HP_GAIN[2:0])" on page 41. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 21 - 24 on page 55. 6. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. 7. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 0.022 F
C
L
R
L
AGND
Figure 3. Headphone Output Test Load
DS723A1
15
CS43L21 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 8)
Frequency Response 10 Hz to 20 kHz Passband StopBand StopBand Attenuation (Note 9) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.05 dB corner to -3 dB corner
Min
-0.01 0 0 0.5465 50 -
Typ
10.4/Fs -
Max
+0.08 0.4780 0.4996 +1.5/+0 +0.05/-0.25 -0.2/-0.4
Unit
dB Fs Fs Fs dB s dB dB dB
Notes: 8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30 on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 9. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL.) Parameters RESET pin Low Pulse Width
MCLK Frequency MCLK Duty Cycle (Note 11) (Note 10)
Symbol
Min
1 1.024 45
Max
38.4 55
Units
ms MHz %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) ts(SD-SK) th 4 8 4 50 45 45 40 20 20 12.5 25 50 100 55 64*Fs 55 kHz kHz kHz kHz % Hz % ns ns ns
LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge
16
DS723A1
CS43L21
//
LRCK
ts(LK-SK) // // // ts(SD-SK) th MSB-1 tP
SCLK
SDIN
// MSB //
Figure 4. Serial Audio Interface Slave Mode Timing
Parameters Master Mode (Note 12)
Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDIN MSB Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge All Speed Modes
Symbol
Min
Max
Units
Fs
45
MCLK ---------------128 55 64*Fs 55 52
Hz % Hz % ns ns ns
1/tP td(MSB) ts(SD-SK) th
45
20 20
-
10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are settled. 11. See "Example System Clock Frequencies" on page 57 for typical MCLK frequencies. 12. See "Master" on page 29
//
LRCK
// tP // // td(MSB) ts(SD-SK) // MSB // th MSB-1
SCLK
SDIN
Figure 5. Serial Audio Interface Master Mode Timing
DS723A1
17
CS43L21 SWITCHING SPECIFICATIONS - IC(R) CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter
SCL Clock Frequency
Symbol
fscl tirs tbuf thdst tlow thigh tsust (Note 13) thdd tsud trc tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 3450
Unit
kHz ns s s s s s s ns s ns s ns
RESET Rising Edge to Start
Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 6. Control Port Timing - IC
18
DS723A1
CS43L21 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter
CCLK Clock Frequency
Symbol
fsck tsrs tcss tcsh tscl tsch tdsu (Note 14) (Note 15) (Note 15) tdh tr2 tf2
Min
0 20 20 1.0 66 66 40 15 -
Max
6.0 100 100
Units
MHz ns ns s ns ns ns ns ns ns
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For fsck <1 MHz.
RST
tsrs
CS
tcsh tcss tsch tscl tr2
CCLK
tf2 tdsu tdh
CDIN
Figure 7. Control Port Timing - SPI Format
DS723A1
19
CS43L21 DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.) Parameters VQ Characteristics
Nominal Voltage Output Impedance DC Current Source/Sink (Note 16) FILT+ 0.5*VA 23 VA 10 V k A V
Min
Typ
Max
Units
VSS_HP Characteristics
Nominal Voltage DC Current Source Power Supply Rejection Ratio (PSRR) (Note 17) 1 kHz -0.8*(VA_HP) 60 10 V A dB
16. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 18)
Input Leakage Current Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) Low-Level Output Voltage (IOL = 100 A) High-Level Input Voltage Low-Level Input Voltage VOH VOL VIH VIL VL - 0.2 0.68*VL 0.2 0.32*VL V V V V
Symbol
Iin
Min
-
Max
10 10
Units
A pF
18. See "Digital I/O Pin Characteristics" on page 8 for serial and control port power rails.
20
DS723A1
CS43L21 POWER CONSUMPTION
See (Note 19) Power Ctl. Registers 02h 03h
Operation PDN_DACB PDN_DACA BIT 4 BIT 3 BIT 2 BIT 1 PDN BIT 3 BIT 2 BIT 1
Typical Current (mA)
iVA_HP
iVA
iVD
iVL (Note 22) 0 0 0 0 0.01 0.02 0.01 0.02
V
0 0 0 0 1.66 2.03 2.77 3.21 0 0 0.01 0.01 1.40 1.71 2.05 2.50 0 0 0.02 0.03 2.35 3.48 2.35 3.49
Total Power (mWrms)
0 0 0.05 0.10 9.74 18.08 12.93 23.02
1 2 5
Off (Note 20) Standby (Note 21) Mono Playback
x x x x x x x x x x 1.8 2.5 x x x x x x 1 x x x 1.8 2.5 1 0 1 1 1 1 0 1 1 1 1.8 2.5 0 0 1 1 1 1 0 1 1 1 1.8 2.5
6
Stereo Playback
19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation. 20. RESET pin 25 held LO, all clocks and data lines are held LO. 21. RESET pin 25 held HI, all clocks and data lines are held HI. 22. VL current will slightly increase in master mode.
DS723A1
21
CS43L21 4. APPLICATIONS
4.1 4.1.1 Overview Architecture
The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2
Line & Headphone Outputs
The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for the headphone amplifier are available.
4.1.3
Signal Processing Engine
A signal processing engine is available to process serial input D/A data before output to the DAC. The D/A data has independent volume controls and mixing functions such as mono mixes and left/right channel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic level control provides limiting capabilities at programmable attack and release rates, maximum thresholds and soft ramping. A 15/50 s de-emphasis filter is also available at a 44.1 kHz sample rate.
4.1.4
Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume may be controlled independently.
4.1.5
Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire IC or three-wire SPI control port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
4.1.6
Power Management
Two Software Mode control registers provide independent power-down control of the DAC, allowing operation in select applications with minimal power consumption.
22
DS723A1
CS43L21
4.2 Hardware Mode
A limited feature-set is available when the D/A powers up in Hardware Mode (see "Recommended PowerUp Sequence" section on page 31) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available. Hardware Mode Feature/Function Summary Feature/Function Default Configuration Stand-Alone Control
Power Control Auto-Detect Speed Mode MCLK Divide Serial Port Master / Slave Selection Interface Control DAC Volume & Gain DAC HP Gain AOUTx Volume Invert Soft Ramp Zero Cross Serial Port Slave Serial Port Master Device DACx Powered Up Powered Up Enabled Auto-Detect Speed Mode Single-Speed Mode (Selectable) (Selectable) (Selectable) G = 0.6047 0 dB Disabled Enabled Disabled (Selectable) Mix Beep Tone Control Peak Detect and Limiter DAC Disabled Disabled Disabled Disabled Data Input (PCM) to DAC PCMA = L; PCMB = R (64xFs)/7 Table 2. Hardware Mode Feature Summary "MCLKDIV2" pin 2 "M/S" pin 29 "IS/LJ" pin 3
Note
see Section 4.4 on page 28 see Section 4.4 on page 28 see Section 4.5 on page 30
-
-
DAC De-Emphasis Signal Processing Engine (SPE)
"DEM" pin 4
see Section on page 24 -
-
Data Selection Channel Mix Charge Pump Frequency
DS723A1
23
CS43L21
4.3 Analog Outputs
AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options are available, including an internal Beep Generator. The desired path to the DAC must be selected using the DATA_SEL[1:0] bits.
Software Controls: "DAC Control (Address 09h)" on page 42.
SIGNAL PROCESSING ENGINE (SPE)
OUTA_VOL[7:0] OUTB_VOL[7:0] +12dB/-102dB 0.5dB steps
ARATE[7:0] RRATE[7:0] MAX[2:0] MIN[2:0] LIM_SRDIS LIM_ZCDIS LIMIT_EN
Chnl Vol. Settings PCM Serial Interface
MUTE_PCMMIXA MUTE_PCMMIXB PCMMIXA_VOL[6:0] PCMMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps
Limiter
DEEMPH
PCMA[1:0] PCMB[1:0]
TC_EN
Peak Detect
DATA_SEL[1:0]
PDN_DACA PDN_DACB
HP_GAIN[2:0]
Demph
VOL
Channel Swap
VOL
VOL
DAC_SZC[1:0] DACA_MUTE DACB_MUTE INV_DACA INV_DACB DAC_SNGVOL AMUTE
Bass/ Treble/ Control
BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] +12.0dB/-10.5dB 1.5dB steps
01 00
Switched Capacitor DAC and Filter
Headphone Amp - GND Centered Charge Pump
Left/Right HP Out
BPVOL[4:0] 0dB/-50dB 2.0dB steps
CHRG_FREQ[3:0]
OFFTIME[2:0] ONTIME[3:0] FREQ[3:0] REPEAT BEEP
Beep Generator
Figure 8. Output Architecture
4.3.1
De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 9. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode.
Software Controls: Hardware Control: "DAC Control (Address 09h)" on page 42. Pin Setting Selection No De-Emphasis De-Emphasis Applied
"DEM" pin 4. LO HI
24
DS723A1
CS43L21
Gain dB
T1=50 s 0dB
T2 = 15 s -10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 9. De-Emphasis Curve
4.3.2
Volume Controls
Two digital volume control functions offer independent control of the SDIN signal path into the mixer as well as a combined control of the mixed signals. The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the DAC_SZC[1:0] bits.
Software Controls: "PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)" on page 44"AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 49"DAC Output Control (Address 08h)" on page 41
4.3.3
Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for the SDIN data. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap.
Software Controls: "PCM Channel Mixer (Address 18h)" on page 49.
4.3.4
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off times are available. Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be required to set the Beep volume sufficiently below the threshold to prevent the peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep volume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits.
Software Controls: "Beep Frequency & Timing Configuration (Address 12h)" on page 45, "Beep Off Time & Volume (Address 13h)" on page 46, "Beep Configuration & Tone Configuration (Address 14h)" on page 47
DS723A1
25
CS43L21
REPEAT = '1' BEEP = '1' CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared.
REPEAT = '1' BEEP = '0'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared. SINGLE-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME. BEEP must be cleared and set for additional beeps.
REPEAT = '0' BEEP = '1'
BPVOL[4:0]
...
FREQ[3:0] ONTIME[3:0] OFFTIME[2:0]
Figure 10. Beep Configuration Options
4.3.5
Tone Control
Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequencies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings.
Software Controls: "Tone Control (Address 15h)" on page 48.
4.3.6
Limiter
When enabled, the limiter monitors the digital input signal before the DAC modulator, detects when levels exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume returns to its original level set in the Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. The "cushion" bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. Note: 1. When the Limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. 2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds.
Software Controls: "Limiter Release Rate Register (Address 1Ah)" on page 51, "Limiter Attack Rate Register (Address 1Bh)" on page 52, "DAC Control (Address 09h)" on page 42
26
DS723A1
CS43L21
Input
MAX[2:0]
Limiter
ATTACK/RELEASE SOUND CUSHION
Volume
AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled.
Output (after Limiter) CUSH[2:0]
MAX[2:0]
ARATE[5:0]
RRATE[5:0]
Figure 11. Peak Detect & Limiter
4.3.7
Line-Level Outputs and Filtering
The CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outputs on AOUTA and AOUTB. These amplifiers are ground centered and do not have any DC offset. A load stabilizer circuit, shown in the "Typical Connection Diagram (Software Mode)" on page 9 and the "Typical Connection Diagram (Hardware Mode)" on page 10, is required on the analog outputs. This allows the DAC amplifiers to drive line or headphone outputs. Also shown in the Typical Connection diagrams is the recommended passive output filter to support higher impedances such as those found on the inputs to operational amplifiers. "Rext", shown in the typical connection diagrams, is the input impedance of the receiving device. The invert and digital gain controls may be used to provide phase and/or amplitude compensation for an external filter. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter.
Software Controls: "DAC Output Control (Address 08h)" on page 41, "AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 49.
DS723A1
27
CS43L21
4.3.8 On-Chip Charge Pump
An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency (bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply, VSS_HP, and may result in clipping. The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. This frequency may be adjusted in the control port registers. Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor connected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple induced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the typical connection diagrams in Figure 1 on page 9 or Figure 2 on page 10 for the recommended capacitor values for the charge pump circuitry.
Software Controls: "Charge Pump Frequency (Address 21h)" on page 53.
4.4
Serial Port Clocking
The D/A serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the M/S and MCLKDIV2 stand-alone control pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the M/S pin is latched immediately after powering up in Hardware Mode. Software Control:
, "DAC Control (Address 09h)" on page 42.
Pin Hardware Control:
"M/S" pin 29
Setting
47 k Pull-down 47 k Pull-up LO Slave Master
Selection
No Divide MCLK is divided by 2 prior to all internal circuitry.
"MCLKDIV2" pin 2
HI
28
DS723A1
CS43L21
4.4.1 Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits. Auto-Detect
Disabled (Software Mode only) Enabled
QSM
512, 768, 1024, 1536, 2048, 3072
HSM
256, 384, 512, 768, 1024, 1536 512, 768, 1024*, 1536*
SSM
128, 192, 256, 384, 512, 768 256, 384, 512*, 768*
DSM
128, 192, 256, 384 128, 192, 256*, 384*
1024, 1536, 2048*, 3072* *MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
4.4.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
/ 128 / 128 / 256 / 512 /1 MCLK /2 1 /2 MCLKDIV2 /2 /4 /8
Double Speed Single Speed Half Speed Quarter Speed Double Speed Single Speed Half Speed Quarter Speed
00 01
LRCK Output (Equal to Fs)
10 11
0 SPEED[1:0]
00 01
SCLK Output
10 11
Figure 12. Master Mode Timing
DS723A1
29
CS43L21
4.4.3 High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a highimpedance state, allowing another device to transmit clocks without bus contention.
CS42L51
Transmitting Device #1
Transmitting Device #2
3ST_SP SCLK/LRCK
Receiving Device
Figure 13. Tri-State SCLK/LRCK
4.4.4
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to SSM.
4.5
Digital Interface Formats
The serial port operates in standard IS, Left-Justified or Right-Justifieddigital interface formats with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK. Figures 14-17 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 16 for exact timing relationship between clocks and data. Software Control: Hardware Control:
"Interface Control (Address 04h)" on page 41.
Pin
"IS/LJ" pin 3
Setting
LO HI Left-Justified Interface IS Interface
Selection
LRCK SCLK SDIN
MSB
L eft C h a n n e l
R ig ht C h a n n el
LSB AOUTA / AINxA
MSB AOUTB / AINxB
LSB
MSB
Figure 14. IS Format
30
DS723A1
CS43L21
LRCK SCLK SDIN
MSB AOUTA / AINxA LS B MSB AOUTB / AINxB LSB
L eft C h a n n e l
R ig ht C h a n n e l
MSB
Figure 15. Left-Justified Format
LRCK SCLK SDIN
L eft C h a n n el
R ig ht C h a n n el
MSB AOUTA
LSB
M SB AOUTB
LS B
Figure 16. Right-Justified Format (DAC only)
4.6
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 32. The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit DAC and switchedcapacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in "Software Mode" on page 33. If a valid write sequence to the control port is not made within approximately 10 ms, the will enter Hardware Mode. Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.7
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable. 2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode. 3. For Software Mode operation, set the PDN bit to `1'b in under 10 ms. This will place the device in "standby". 4. Load the desired register settings while keeping the PDN bit set to `1'b. 5. Start MCLK to the appropriate frequency, as discussed in Section 4.4. 6. Set the PDN bit to `0'b. 7. Apply LRCKSCLK and SDIN for normal operation to begin. 8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
DS723A1
31
CS43L21
4.8 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the D/A in standby, 1. Mute the DAC's. 2. Set the PDN bit in the power control register to `1'b. The D/A will not power down until it reaches a fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. Bring RESET low.
No Power 1. No audio signal generated.
Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default.
PDN bit = '1'b?
Yes
Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings.
No No RESET = Low? Yes Valid MCLK Applied?
No
20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged.
Initialization 50 ms delay No Control Port Valid Write Seq. within 10 ms? Yes
Digital/Analog Output Muted
Charge Pump Powered Up Headphone Amp Powered Down
Power Off Transition 1. Audible pops.
Hardware Mode Minimal feature set support.
Software Mode Registers setup to desired settings.
Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed.
20 s delay 20 s delay Headphone Amp Powered Up Stand-By Transition 1. Pops suppressed.
Reset Transition 1. Pops suppressed.
No Valid MCLK/LRCK Ratio? Yes
RESET = Low ERROR: MCLK/LRCK ratio change ERROR: Power removed
Normal Operation Audio signal generated per control port or standalone settings.
PDN bit set to '1'b (software mode only)
ERROR: MCLK removed
Analog Output Freeze 1. Aout bias = last audio sample. 2. DAC Modulators stop operation. 3. Audible pops.
Figure 17. Initialization Flow Chart
32
DS723A1
CS43L21
4.9 Software Mode
The control port is used to access the registers allowing the D/A to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in two modes: SPI and IC, with the D/A acting as a slave device. Software Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit address state.
4.9.1
SPI Control
In Software Mode, CS is the CS43L21 chip-select signal, CCLK is the control port bit clock (input into the from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The D/A will only support write operations. Read request will be ignored. Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +n
6 1 0
CDIN
1
0
0
1
0
1
0
6
5
4
3
Figure 18. Control Port Timing in SPI Mode
4.9.2
IC Control
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS43L21 is being reset. The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS43L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS43L21, the chip address field, which is the first byte sent to the CS43L21, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-
DS723A1
33
CS43L21
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS43L21 after each input byte is read and is input to the CS43L21 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
0
1
AD0
6
5
4
3
ACK START
ACK
ACK
ACK STOP
Figure 19. Control Port Timing, IC Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
0 1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 20. Control Port Timing, IC Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto-increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100101x1 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
34
DS723A1
CS43L21
4.9.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details.
4.9.3.1
Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
DS723A1
35
CS43L21 5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. "Reserved" registers must maintain their default state.
Addr
01h
Function
ID p 39 default
7
Chip_ID4 1 Reserved 0
6
Chip_ID3 1
5
Chip_ID2 0
4
Chip_ID1 1
3
Chip_ID0 1
2
Rev_ID2 0
1
Rev_ID1 0
0
Rev_ID0 1 PDN 0
02h
Power Ctl. 1 p 39 default
PDN_DACB PDN_DACA 0 0
Reserved
Reserved
Reserved
Reserved
1(See Note 1(See Note 1(See Note 1(See Note 2 on page 2 on page 2 on page 2 on page 39) 39) 39) 39)
3-ST_SP 0 DAC_DIF1 0
03h
Speed Ctl. & Power Ctl. 2 p 40 default
AUTO 1
SPEED1 0 M/S 0
SPEED0 1 DAC_DIF2 0
Reserved
1 DAC_DIF0 0
Reserved
1
Reserved
1
MCLKDIV2 0
04h
Interface Ctl. p 41 default
Reserved
0
Reserved
0
Reserved
0
Reserved
0
05h
Reserved
default
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
06h
Reserved
default
Reserved
1
Reserved
0
Reserved
1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
07h
Reserved
Reserved
0
Reserved
0 HP_GAIN1 1 DATA_SEL0 0
Reserved
0 HP_GAIN0 1 FREEZE 0 Reserved 0 Reserved 0
Reserved
0 DAC_SNG VOL 0 Reserved 0
Reserved
0 INV_PCMB 0 DEEMPH 0
Reserved
0 INV_PCMA 0 AMUTE 1
Reserved
0 DACB_ MUTE 0 DAC_SZC1 1
Reserved
0 DACA_ MUTE 0 DAC_SZC0 0
default 08h DAC Output Control p 41 default 09h DAC Control p 42 default 0Ah HP_GAIN2 0 DATA_SEL1 0
Reserved
default
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
0Bh
Reserved
default
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
0Ch Reserved default 0Dh Reserved default 0Eh
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
default
Reserved
1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
36
DS723A1
CS43L21
Addr
0Fh
Function Reserved
default
7 Reserved
1
6 Reserved
0 PCMMIXA VOL6 0 PCMMIXB VOL6 0 FREQ2 0 OFFTIME1 0 BEEP
5 Reserved
0 PCMMIXA VOL5 0 PCMMIXB VOL5 0 FREQ1 0 OFFTIME0 0 Reserved
4 Reserved
0 PCMMIXA VOL4 0 PCMMIXB VOL4 0 FREQ0 0 BPVOL4 0 TREB_CF1
3 Reserved
0 PCMMIXA VOL3 0 PCMMIXB VOL3 0 ONTIME3 0 BPVOL3 0 TREB_CF0
2 Reserved
0 PCMMIXA VOL2 0 PCMMIXB VOL2 0 ONTIME2 0 BPVOL2 0 BASS_CF1
1 Reserved
0 PCMMIXA VOL1 0 PCMMIXB VOL1 0 ONTIME1 0 BPVOL1 0 BASS_CF0
0 Reserved
0 PCMMIXA VOL0 0 PCMMIXB VOL0 0 ONTIME0 0 BPVOL0 0 TC_EN
10h
Vol. Control PCMMIXA p 44 default
MUTE_PCM MIXA 1 MUTE_PCM MIXB 1 FREQ3 0 OFFTIME2 0 REPEAT
11h
Vol. Control PCMMIXB p 44 default
12h
BEEP Freq. & OnTime p 45 default
13h
BEEP Off Time & Vol p 46 default
14h
BEEP Control & Tone Config p 47 default
0 TREB3 1 AOUTA_ VOL7 0 AOUTB_ VOL7 0 PCMA1 0 MAX2
0 TREB2 0 AOUTA_ VOL6 0 AOUTB_ VOL6 0 PCMA0 0 MAX1
0 TREB1 0 AOUTA_ VOL5 0 AOUTB_ VOL5 0 PCMB1 0 MAX0
0 TREB0 0 OUTA_ VOL4 0 AOUTB_ VOL4 0 PCMB0 0 CUSH2
0 BASS3 1 AOUTA_ VOL3 0 AOUTB_ VOL3 0
0 BASS2 0 AOUTA_ VOL2 0 AOUTB_ VOL2 0
0 BASS1 0 AOUTA_ VOL1 0 AOUTB_ VOL1 0
0 BASS0 0 AOUTA_ VOL0 0 AOUTB_ VOL0 0
15h
Tone Control p 48 default
16h
Vol. Control AOUTA p 49 default
17h
Vol. Control AOUTB p 49 default
18h
PCM Channel Mixer p 49 default
Reserved
0 CUSH1
Reserved
0 CUSH0
Reserved
0 LIM_SRDIS
Reserved
0 LIM_ZCDIS
19h
Limiter Threshold & SZC Disable p 50 default
0 LIMIT_EN
0 LIMIT_ALL
0 LIM_RRATE 5
0 LIM_RRATE 4
0 LIM_RRATE 3
0 LIM_RRATE 2
0 LIM_RRATE 1
0 LIM_RRATE 0
1Ah
Limiter Config & Release Rate p 51 default
0
Reserved 0
1
Reserved 0
1
1
1
1
1
1
1Bh
Limiter Attack Rate p 52 default
LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 0 0 0 0 0 0
1Ch Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DS723A1
37
CS43L21
Addr Function
default 1Dh Reserved default 1Eh Reserved default 1Fh Reserved default 20h Status p 52 default 21h p 53 default Reserved 0 CHRG_ FREQ3 0 SP_CLKER SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL R 0 CHRG_ FREQ2 1 0 CHRG_ FREQ1 0 0 CHRG_ FREQ0 1 0 Reserved 0 0 Reserved 0 Reserved 0 Reserved 0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reserved
1
Reserved
1
Reserved
1
Reserved
1
Reserved
1 Reserved 0
Reserved
1 Reserved 0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0 Reserved 0
Reserved
0 Reserved 0
38
DS723A1
CS43L21 6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All "Reserved" registers must maintain their default state.
6.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
6 Chip_ID3 5 Chip_ID2 4 Chip_ID1 3 Chip_ID0 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0
7 Chip_ID4
Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS43L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2
Power Control 1 (Address 02h)
6 PDN_DACB 5 PDN_DACA 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 PDN
7 Reserved
Notes: 1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the D/A has fully powered up will mute the selected channel without achieving any power savings. 2. Reserved bits 1 - 4 should always be set "high" by the user to minimize power consumption during normal operation. Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit. Power Down DAC X (PDN_DACX) Default: 0 0 - Disable 1 - Enable Function: DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above.
DS723A1
39
CS43L21
Power Down (PDN) Default: 0 0 - Disable 1 - Enable Function: The entire D/A will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode.
6.3
Speed Control (Address 03h)
7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 Reserved 2 Reserved 1 Reserved 0 MCLKDIV2
Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the D/A when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 29. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the D/A in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above). Tri-State Serial Port Interface (3ST_SP) Default: 0 0 - Disable 1 - Enable Function: When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-impedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs. MCLK Divide By 2 (MCLKDIV2) Default: 0 0 - Disabled 1 - Divide by 2 40 DS723A1
CS43L21
Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode.
6.4
Interface Control (Address 04h)
6 M/S 5 DAC_DIF2 4 DAC_DIF1 3 DAC_DIF0 2 Reserved 1 Reserved 0 Reserved
7 Reserved
Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port. DAC Digital Interface Format (DAC_DIF[2:0]) Default = 000 DAC_DIF[2:0] 000 001 010 011 100 101 110 100 Function: Selects the digital interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "Digital Interface Formats" on page 30. Description Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data Right-Justified, 16-bit data Reserved Reserved Figure 15 on page 31 14 on page 30 17 on page 3217 on page 32 17 on page 3217 on page 32 17 on page 3217 on page 32 17 on page 3217 on page 32 -
6.5
7
DAC Output Control (Address 08h)
6 HP_GAIN1 5 HP_GAIN0 4 DAC_ SNGVOL 3 INV_PCMB 2 INV_PCMA 1 0 DACB_MUTE DACA_MUTE
HP_GAIN2
Headphone Analog Gain (HP_GAIN[2:0]) Default: 011 HP_GAIN[2:0]
000 001 010 011 100 101 110 111
Gain Setting
0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430
DS723A1
41
CS43L21
Function: These bits select the gain multiplier for the headphone/line outputs. See "Line Output Voltage Characteristics" on page 14 and "Headphone Output Power Characteristics" on page 15. DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUTA Volume Control register and the AOUTB Volume Control register is ignored. PCMX Invert Signal Polarity (INV_PCMX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the PCM x channel. DACX Channel Mute (DACX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]).
6.6
DAC Control (Address 09h)
6 DATA_SEL0 5 FREEZE 4 Reserved 3 DEEMPH 2 AMUTE 1 DAC_SZC1 0 DAC_SZC0
7 DATA_SEL1
DAC Data Selection (DATA_SEL[1:0]) Default: 00 00 - PCM Serial Port to DAC 01 - Signal Processing Engine to DAC 10 - Reserved 11 - Reserved Function: Selects the digital signal source for the DAC. Note: Certain functions are only available when the "Signal Processing Engine to DAC" option is selected using these bits.
42
DS723A1
CS43L21
Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. DAC De-Emphasis Control (DEEMPH) Default: 0 0 - No De-Emphasis 1 - De-Emphasis Enabled Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control. Enables the digital filter to apply the standard 15s/50s digital de-emphasis filter response for a sample rate of 44.1 kHz. Analog Output Auto MUTE (AMUTE) Default: 0 0 - Auto Mute Disabled 1 - Auto Mute Enabled Function: Enables (or disables) Automatic Mute of the analog outputs after 8192 "0" samples on each digital input channel. DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. DS723A1 43
CS43L21
Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.7
PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)
6 PCMMIXx_ VOL6 5 PCMMIXx_ VOL5 4 PCMMIXx_ VOL4 3 PCMMIXx_ VOL3 2 PCMMIXx_ VOL2 1 PCMMIXx_ VOL1 0 PCMMIXx_ VOL0
7 MUTE_ PCMMIXx
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. PCMX Mixer Channel Mute (MUTE_PCMMIXX) Default = 1 0 - Disabled 1 - Enabled Function: The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]). PCMX Mixer Volume Control (PCMMIXX_VOL[6:0]) Default: 000 0000 Binary Code
001 1000 *** 000 0000 111 1111 111 1110 *** 001 1001
Volume Setting
+12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -51.5 dB
Function: The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described in the table above.
44
DS723A1
CS43L21
6.8 Beep Frequency & Timing Configuration (Address 12h)
6 FREQ2 5 FREQ1 4 FREQ0 3 ONTIME3 2 ONTIME2 1 ONTIME1 0 ONTIME0 7 FREQ3
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Frequency (FREQ[3:0]) Default: 0000 FREQ[3:0] Frequency Pitch Fs = 12, 24, 48 or 96 kHz
260.87 Hz 521.74 Hz 585.37 Hz 666.67 Hz 705.88 Hz 774.19 Hz 888.89 Hz 1000.00 Hz 1043.48 Hz 1200.00 Hz 1333.33 Hz 1411.76 Hz 1600.00 Hz 1714.29 Hz 2000.00 Hz 2181.82 Hz C4 C5 D5 E5 F5 G5 A5 B5 C6 D6 E6 F6 G6 A6 B6 C7
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Function: The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits. Beep On Time Duration (ONTIME[3:0]) Default: 0000 TIME[3:0]
0000 *** 1111
On Time Fs = 12, 24, 48 or 96 kHz
86 ms *** 5.2 s
Function: The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits.
DS723A1
45
CS43L21
6.9 Beep Off Time & Volume (Address 13h)
6 OFFTIME1 5 OFFTIME0 4 BPVOL4 3 BPVOL3 2 BPVOL2 1 BPVOL1 0 BPVOL0 7 OFFTIME2
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 OFFTIME[2:0] Off Time Fs = 12, 24, 48 or 96 kHz
1.23 s 2.58 s 3.90 s 5.20 s 6.60 s 8.05 s 9.35 s 10.80 s
000 001 010 011 100 101 110 111
Function: The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Beep Volume (BPVOL[4:0]) Default: 00000 Binary Code
00110 *** 00000 11111 11110 *** 00111
Volume Setting
+12.0 dB *** 0 dB -2 dB -4 dB *** -50 dB
Function: The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Levels are decoded as described in the table above.
46
DS723A1
CS43L21
6.10 Beep Configuration & Tone Configuration (Address 14h)
6 BEEP 5 Reserved 4 TREB_CF1 3 TREB_CF0 2 BASS_CF1 1 BASS_CF0 0 TC_EN 7 REPEAT
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Repeat Beep (REPEAT) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output. Refer to Figure 10 on page 26 for a description of each configuration option. Beep (BEEP) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration. Refer to Figure 10 on page 26 for a description of each configuration option. Treble Corner Frequency (TREB_CF[1:0]) Default: 00 00 - 5 kHz 01 - 7 kHz 10 - 10 kHz 11 - 15 kHz Function: The treble corner frequency is user selectable as shown above. Bass Corner Frequency (BASS_CF[1:0]) Default: 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - 250 Hz Function: The bass corner frequency is user-selectable as shown above.
DS723A1
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CS43L21
Tone Control Enable (TC_EN) Default = 0 0 - Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled.
6.11
Tone Control (Address 15h)
6 TREB2 5 TREB1 4 TREB0 3 BASS3 2 BASS2 1 BASS1 0 BASS0
7 TREB3
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Treble Gain Level (TREB[3:0]) Default: 1000 dB (No Treble Gain) Binary Code
0000 *** 0111 1000 1001 *** 1111
Gain Setting
+12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB
Function: The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB. Bass Gain Level (BASS[3:0]) Default: 1000 dB (No Bass Gain) Binary Code
0000 *** 0111 1000 1001 *** 1111
Gain Setting
+12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB
Function: The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB increments from +10.5 to -10.5 dB.
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CS43L21
6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)
7 6 5 4 3 2 1 0 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. AOUTX Volume Control (AOUTX_VOL[7:0]) Default = 00h Binary Code
0001 1000 *** 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001
Volume Setting
+12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB
Function: The analog output levels can be adjusted in 0.5 dB increments from +12 to -102 dB as dictated by the DAC Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table above. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits.
6.13
PCM Channel Mixer (Address 18h)
6 PCMA0 5 PCMB1 4 PCMB0 3 Reserved 2 Reserved 1 Reserved 0 Reserved
7 PCMA1
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Channel Mixer (PCMx[1:0]) Default: 00 PCMA[1:0]
00 01 10 11
AOUTA
L L+R ----------2 R
PCMB[1:0]
00 01 10 11
AOUTB
R L+R ----------2 L
Function: Implements mono mixes of the left and right channels as well as a left/right channel swap.
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CS43L21
6.14 Limiter Threshold SZC Disable (Address 19h)
6 MAX1 5 MAX0 4 CUSH2 3 CUSH1 2 CUSH0 1 LIM_SRDIS 0 LIM_ZCDIS 7 MAX2
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Maximum Threshold (MAX[2:0]) Default: 000
MAX[2:0] Threshold Setting (dB)
000 001 010 011 101 101 110 111 0 -3 -6 -9 -12 -18 -24 -30
Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate. Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. Cushion Threshold (CUSH[2:0]) Default: 000
CUSH[2:0] Threshold Setting (dB)
000 001 010 011 101 101 110 111 0 -3 -6 -9 -12 -18 -24 -30
Function: Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0]) threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter attacks and releases.
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Limiter Soft Ramp Disable (LIM_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = `01'b or `11'b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the zero-cross setting.
6.15
Limiter Release Rate Register (Address 1Ah)
6 LIMIT_ALL 5 RRATE5 4 RRATE4 3 RRATE3 2 RRATE2 1 RRATE1 0 RRATE0
7 LIMIT_EN
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Peak Detect and Limiter Enable (LIMIT_EN) Default: 0 0 - Disabled 1 - Enabled Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. Peak Signal Limit All Channels (LIMIT_ALL) Default: 1 0 - Individual Channel 1 - Both channel A & B Function: When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping.
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CS43L21
Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Binary Code
000000 *** 111111
Release Time
Fastest Release *** Slowest Release
Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting. The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled.
6.16
Limiter Attack Rate Register (Address 1Bh)
6 Reserved 5 ARATE5 4 ARATE4 3 ARATE3 2 ARATE2 1 ARATE1 0 ARATE0
7 Reserved
Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Limiter Attack Rate (ARATE[5:0]) Default: 000000 Binary Code
000000 *** 111111
Attack Time
Fastest Attack *** Slowest Attack
Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled.
6.17
Status (Address 20h) (Read Only)
6 SP_CLKERR 5 SPEA_OVFL 4 SPEB_OVFL 3 2 PCMA_OVFL PCMB_OVFL 1 Reserved 0 Reserved
7 Reserved
For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A "0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See "Serial Port Clocking" section on page 28"Serial Port Clocking" on page 28 for valid clock ratios. Note: 52 On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. DS723A1
CS43L21
Signal Processing Engine Overflow (SPEX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path after the signal processing engine. PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM mix.
6.18
Charge Pump Frequency (Address 21h)
3 Reserved 2 Reserved 1 Reserved 0 Reserved
7 6 5 4 CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ 3 2 1 0
Charge Pump Frequency (CHRG_FREQ[3:0]) Default: 0101 N
0 ... 15
CHRG_FREQ[3:0]
0000 ... 1111
Frequency 64xFs ---------------N+2
Function: Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band. Note: Distortion performance may be affected.
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CS43L21 7. ANALOG PERFORMANCE PLOTS
7.1 Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB43L21 using an Audio Precision analyzer.
-10
G = 0.6047
-15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0
VA_HP = VA = 1.8 V
G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend
d B r A
NOTE: Graph shows the output power per channel (i.e. Output Power = 23 mW into single 16 and 46 mW into stereo 16 with THD+N = 75 dB).
10m
20m
30m
40m W
50m
60m
70m
80m
Figure 21. THD+N vs. Output Power per Channel at 1.8 V (16 load)
-10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0
G = 0.6047
VA_HP = VA = 2.5 V
G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend
d B r A
NOTE: Graph shows the output power per channel (i.e. Output Power = 44 mW into single 16 and 88 mW into stereo 16 with THD+N = 75 dB).
10m
20m
30m
40m W
50m
60m
70m
80m
Figure 22. THD+N vs. Output Power per Channel at 2.5 V (16 load)
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CS43L21
G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000
-40 -45
VA_HP = VA = 1.8
-20 -30
-35
G = 1.1430 Legend
-50
-55 d B r A -65
-60
-70
-75
NOTE: Graph shows the output power per channel (i.e. Output Power = 22 mW into single 32 and 44 mW into stereo 32 with THD+N = 75 dB).
-80
-85
-90
-95
-100 0
6m
12m
18m
24m
30m W
36m
42m
48m
54m
60m
Figure 23. THD+N vs. Output Power per Channel at 1.8 V (32 load)
-20
VA_HP = VA = 2.5 V
-25 -30
G = 0.6047 G = 0.7099 G = 0.8399
-35
G = 1.0000
-40 -45
G = 1.1430 Legend
-50
-55 d B r A -65
-60
-70
-75
-80
NOTE: Graph shows the output power per channel (i.e. Output Power = 42 mW into single 32 and 84 mW into stereo 32 with THD+N = 75 dB).
-85
-90
-95
-100 0
5m
10m
15m
20m
25m
30m W
35m
40m
45m
50m
55m
60m
Figure 24. THD+N vs. Output Power per Channel at 2.5 V (32 load)
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CS43L21
7.2 Headphone Amplifier Efficiency
The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback w/16 load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power.
VA_HP = VA = 1.8 V
Figure 25. Power Dissipation vs. Output Power into Stereo 16
VA_HP = VA = 1.8 V
Figure 26. Power Dissipation vs. Output Power into Stereo 16 (Log Detail)
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CS43L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
Sample Rate LRCK (kHz)
8 11.025 12
1024x
8.1920 11.2896 12.2880
MCLK (MHz) 1536x 2048x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
3072x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
512x
8.1920 11.2896 12.2880
MCLK (MHz) 768x 1024x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
1536x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
MCLK (MHz) 384x 512x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
768x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
192x
MCLK (MHz) 256x*
16.3840 22.5792 24.5760
384x*
24.5760 33.8688 36.8640
12.2880 16.9344 18.4320
*The"MCLKDIV2" pin 4 must be set HI.
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CS43L21
8.2 Auto Detect Disabled
Sample Rate LRCK (kHz)
8 11.025 12
512x
6.1440
768x
6.1440 8.4672 9.2160
MCLK (MHz) 1024x 1536x
8.1920 11.2896 12.2880 12.2880 16.9344 18.4320
2048x
16.3840 22.5792 24.5760
3072x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
256x
6.1440
384x
6.1440 8.4672 9.2160
512x
8.1920 11.2896 12.2880
MCLK (MHz) 768x
12.2880 16.9344 18.4320
1024x
16.3840 22.5792 24.5760
1536x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
MCLK (MHz) 384x 512x
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
768x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
192x
MCLK (MHz) 256x
16.3840 22.5792 24.5760
384x
24.5760 33.8688 36.8640
12.2880 16.9344 18.4320
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CS43L21 9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-resolution converter, the CS43L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS43L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS43L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS43L21 evaluation board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS43L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS43L21 evaluation board demonstrates the optimum thermal pad and via configuration.
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CS43L21 10.DIGITAL FILTERS
Figure 27. Passband Ripple
Figure 28. Stopband
Figure 29. Transition Band
Figure 30. Transition Band (Detail)
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CS43L21 11.PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS43L21 12.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
D b e Pin #1 Corner
Pin #1 Corner
E
E2
A1 A Top View Side View
L
D2
Bottom View
DIM
A A1 b D D2 E E2 e L
MIN
-0.0000 0.0071 0.1280 0.1280 0.0118
INCHES NOM
--0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157
MAX
0.0394 0.0020 0.0110 0.1319 0.1319 0.0197
MIN
-0.00 0.18 3.25 3.25 0.30
MILLIMETERS NOM
--0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40
NOTE MAX
1.00 0.05 0.28 3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1
JEDEC #: MO-220 Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board
Symbol
JA
Min
-
Typ
52 38
Max
-
Units
C/Watt
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CS43L21 13.ORDERING INFORMATION
Product
CS43L21
Description
Low-Power Stereo D/A with HP Amp for Portable Apps CS43L21 Evaluation Board
Package Pb-Free
32L-QFN Yes
Grade
Temp Range
Container
Order #
Commercial -10 to +70 C Automotive No -40 to +85 C -
Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR CDB43L21
CDB43L21
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 3. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 4. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
15.REVISION HISTORY
Revision
A1 Initial Release
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
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